A field effect transistor (FET) is a device in which regions called a source and a drain are provided in a semiconductor, each of the regions is provided with an electrode, potentials are supplied to the electrodes, and an electric field is applied to the semiconductor with the use of an electrode called a gate through an insulating film or a Schottky barrier so that the state of the semiconductor is controlled, whereby current flowing between the source and the drain is controlled. As the semiconductor, Group IV elements (Group 14 elements) such as silicon and germanium, Group III-V compounds such as gallium arsenide, indium phosphide, and gallium nitride, Group II-VI compounds such as zinc sulfide and cadmium telluride, and the like can be given.
In recent years, FETs in which an oxide such as zinc oxide or an indium gallium zinc oxide-based compound is used as a semiconductor have been reported (Patent Document 1 and Patent Document 2). In an FET including such an oxide semiconductor, relatively high mobility can be obtained, and such a material has a wide bandgap of greater than or equal to 3 electron volts; therefore, application of the FET including an oxide semiconductor to displays, power devices, and the like is discussed.
The fact that the bandgap of such a material is greater than or equal to 3 electron volts means that the material transmits visible light, for example; thus, in the case where the material is used in a display, even an FET portion can transmit light and the aperture ratio is expected to be improved.
Further, such a wide bandgap is common to silicon carbide, which is used in power devices; therefore, the oxide semiconductor is also expected to be applied to a power device.
Furthermore, a wide bandgap means few thermally excited carriers. For example, silicon has a bandgap of 1.1 electron volts at room temperature and thus thermally excited carriers exist therein at approximately 1011/cm3, while in a semiconductor with a bandgap of 3.2 electron volts, thermally excited carriers exist at approximately 10−7/cm3 according to calculation.
In the case of silicon, carriers generated by thermal excitation exist as described above even in silicon including no impurities, and thus the resistivity of the silicon cannot be higher than or equal to 105 Ωcm. In contrast, in the case of the semiconductor with a bandgap of 3.2 electron volts, a resistivity of higher than or equal to 1020 Ωcm can be obtained in theory. When an FET is manufactured using such a semiconductor and its high resistivity in an off state (a state where the potential of a gate is the same as the potential of a source) is utilized, it is expected that electric charge can be retained semipermanently.
Meanwhile, there are few reports on an oxide semiconductor which includes zinc or indium in particular and has p-type conductivity. Accordingly, an FET of an oxide semiconductor using a PN junction like an FET of silicon has not been reported, and a conductor-semiconductor junction as disclosed in Patent Document 1 and Patent Document 2, where a conductor electrode is in contact with an n-type oxide semiconductor, has been used for forming a terminal corresponding to a source or a drain.
Note that in general academic books about semiconductors, the “conductor-semiconductor junction” is expressed as a “metal-semiconductor junction.” In this case, metal means a conductor. For example, a semiconductor such as silicon (a degenerated semiconductor in particular) which is doped at a high concentration and whose resistivity is significantly lowered, metal nitrides such as titanium nitride and tungsten nitride, metal oxides such as indium tin oxide and aluminum zinc oxide, and the like are also regarded as metal in “metal-semiconductor junctions.” However, in such a case, the term “metal” might cause misunderstanding; therefore, the term “conductor-semiconductor junction” is used instead of the term “metal-semiconductor junction” in this specification.
In an FET where terminals corresponding to a source and a drain are formed with the use of a conductor-semiconductor junction, when the carrier concentration of the semiconductor is high, current (off-state current) flows between the source electrode and the drain electrode even in an off state. Thus, the off-state current needs to be reduced by lowering the concentration of a donor or an acceptor in the semiconductor so that an i-type semiconductor is obtained. Note that in this specification, an i-type semiconductor is a semiconductor whose carrier concentration derived from a donor or an acceptor is lower than or equal to 1012/cm3. However, it is apparent from the following that such an attempt does not work when the channel length of an FET is short and a semiconductor layer is thick.
In a conductor-semiconductor junction, in general, an ohmic junction or a Schottky barrier junction is formed depending on the relation between a work function of a conductor and an electron affinity (or a Fermi level) of a semiconductor. For example, if an ideal conductor-semiconductor junction (i.e., a junction where a compound, a trap level, or the like does not exist at the interface) is formed by making a conductor with a work function of 3.9 electron volts in contact with a semiconductor with an electron affinity of 4.3 electron volts, electrons flow from the conductor into a region which is in the semiconductor and has a certain width.
In that case, a region closer to a junction interface between the conductor and the semiconductor has a higher electron concentration, and the electron concentrations are 1020/cm3 at several nanometers from the interface of the conductor-semiconductor junction, 1018/cm3 at several tens of nanometers from the interface, 1016/cm3 at several hundreds of nanometers from the interface, and 1014/cm3 even at several micrometers from the interface according to rough calculation. That is, even when the semiconductor itself is an i-type semiconductor, contact with a conductor produces a region with a high carrier concentration. As a result of formation of such a region including many carriers in the vicinity of the interface of the conductor-semiconductor junction, the conductor-semiconductor junction becomes an ohmic junction.
In contrast, for example, if an ideal conductor-semiconductor junction is formed by making a conductor with a work function of 4.9 electron volts in contact with a semiconductor with an electron affinity of 4.3 electron volts, electrons existing in a region which is in the semiconductor and has a certain width move to the conductor. In a region which the electrons have left, the electron concentration is, as is obvious, extremely low. The width of the region of the semiconductor to which electrons move depends on the electron concentration of the semiconductor; for example, when an original electron concentration of the semiconductor is 1018/cm3, the width is several tens of nanometers.
The electron concentration in this portion becomes significantly low; accordingly, a barrier is formed at a junction interface between the conductor and the semiconductor in a band diagram. A conductor-semiconductor junction including such a barrier is referred to as a Schottky barrier junction. Electrons easily flow from the semiconductor to the conductor, whereas electrons are less likely to flow from the conductor to the semiconductor owing to the barrier. Therefore, rectification action is observed in the Schottky barrier junction.
A similar phenomenon occurs even when a conductor is not in direct contact with a semiconductor. For example, even in the case where an insulating film is provided between a semiconductor and a conductor, the electron concentration of the semiconductor is influenced by the conductor. Needless to say, the degree of the influence of the conductor depends on the thickness or the dielectric constant of the insulating film. When the thickness of the insulating film is increased or when the dielectric constant thereof is lowered, the influence of the conductor is reduced.
In an FET, since it is preferable that a junction between a source electrode and a semiconductor or between a drain electrode and the semiconductor be formed so that current flows easily, a material of the source electrode or the drain electrode is selected so that an ohmic junction is formed. For example, titanium and titanium nitride are given. When a junction between an electrode and a semiconductor is an ohmic junction, there are advantages of stable characteristics of an FET to be obtained and of high percentage of non-defective products.
As a material of a gate, a material having action that eliminates electrons from a semiconductor is selected. For example, tungsten and platinum are given. When such a material is used and a ratio L/T, where L is the size of a semiconductor (typically, the distance between a source electrode and a drain electrode) and T is the sum of the effective thicknesses of a gate insulating film and the semiconductor, is greater than or equal to 10, an FET having an extremely small off-state current of less than or equal to 1×10−18 A can be manufactured. Here, T is calculated by the following formula: T=(the thickness of a gate insulating film×the dielectric constant of a semiconductor/the dielectric constant of the gate insulating film)+the thickness of the semiconductor.
The ratio L/T is required to be low because of a need to increase current in an on state (on-state current), a limit of a technique of forming a thin film, miniaturization, or the like. When a semiconductor layer is made thicker, for example, the cross-sectional area thereof is increased; thus, larger current can flow. Further, when the thickness of a semiconductor layer or a gate insulating layer is reduced to the limit of mass production and a channel (the distance between the source electrode and the drain electrode) is shortened, L becomes small relative to T. In addition, for an application to a power device, the thickness of the gate insulating film needs to be increased in order to increase withstand voltage.
With such a structure, however, it is impossible to keep the off-state current low when the ratio L/T is less than or equal to 4. A similar phenomenon can be observed when L is less than 100 nm or when T is greater than or equal to 1 μm. A cause of that phenomenon is described with reference to FIGS. 7A and 7B. FIG. 7A illustrates a typical structure of an FET including a conductor-semiconductor junction. Specifically, a source electrode 13a and a drain electrode 13b are provided on one surface of a semiconductor layer 11. Further, a gate insulating film 14 and a gate 15 are provided over an opposite surface of the semiconductor layer 11.
As the source electrode 13a and the drain electrode 13b, a conductor is selected so that a junction between the source electrode 13a and the semiconductor layer 11 and a junction between the drain electrode 13b and the semiconductor layer 11 are ohmic junctions. By using a material whose work function is higher than the electron affinity of the semiconductor for the gate 15, electrons flowing from the source electrode 13a or the drain electrode 13b are eliminated.
In order to simplify the explanation, it is assumed that a force of the source electrode 13a or the drain electrode 13b for injecting electrons into the semiconductor layer 11 is equal to a force of the gate 15 for eliminating electrons from the semiconductor layer 11. The forces are thought to depend on respective distances from the source electrode 13a (or the drain electrode 13b) and the gate 15 to a point.
In a portion of the semiconductor layer 11 where the distances from the source electrode 13a (or the drain electrode 13b) and the gate 15 are equal, the opposing forces are balanced; therefore, it can be thought that the electron concentration therein is equal to an original value. When the distance from the source electrode 13a is shorter than the distance from the gate 15 in a position, the force of the source electrode 13a is stronger than that of the gate 15; thus, the electron concentration is higher at the position. In contrast, when the former distance is longer than the latter distance in another position, the force of the gate 15 is stronger than that of the source electrode 13a; thus, the electron concentration is lower at the position.
Here, it should be noted that the distance in this case means not a spatial distance but an electromagnetic distance; therefore, the comparison needs to be made on the basis of a value obtained by multiplying a spatial distance by a dielectric constant.
FIG. 7B illustrates conceptual isoconcentration lines of the electron concentration in the semiconductor layer 11 of the FET in FIG. 7A, which is based on the above premise. In order to simplify the explanation, the dielectric constant of the gate insulating film 14 is assumed to be equal to the dielectric constant of the semiconductor layer 11. In addition, the potentials of the source electrode 13a and the drain electrode 13b are equal to the potential of the gate 15.
There are regions 1a where the electron concentration is high in the vicinity of an interface between the semiconductor layer 11 and the source electrode 13a and the drain electrode 13b. Further, regions 1b where the electron concentration is lower than the electron concentration in the regions 1a by approximately one order of magnitude, regions 1c where the electron concentration is lower than that in the regions 1b by approximately one order of magnitude, a region 1d where the electron concentration is lower than that in the regions 1c by approximately one order of magnitude, and a region 1e where the electron concentration is lower than that in the region 1d exist outside the regions 1a in this order.
It should be noted that the region 1d is not divided on a side opposite to the gate 15 in the semiconductor layer 11. This is because the force of the gate 15 does not reach that region and electrons are injected by the forces of the source electrode 13a and the drain electrode 13b. 
In the drawing, the ratio L/T is a little less than 2. Assuming that the distance between the source electrode 13a and the drain electrode 13b is 120 nm, the thickness of the semiconductor layer 11 is 50 nm; thus, the electron concentration on the isoconcentration line between the region 1a and the region 1b is approximately 1020/cm3, and the electron concentration on the isoconcentration line between the region 1d and the region 1e is approximately 1017/cm3.
Assuming that the distance between the source electrode 13a and the drain electrode 13b is 1.2 μm, the thickness of the semiconductor layer 11 is 0.5 μm; thus, the electron concentration on the isoconcentration line between the region 1a and the region 1b is approximately 1018/cm3, and the electron concentration on the isoconcentration line between the region 1d and the region 1e is approximately 1015/cm3.
Although an electron concentration of 1015/cm3 seems low enough, the value is approximately 1 kΩcm in resistivity. As illustrated in the drawing, in one third or more part of the semiconductor layer, the electron concentration is higher than or equal to 1015/cm3. Accordingly, in an FET in which the channel length and the channel width are equal, the resistance is approximately 10 MΩ and the off-state current is as large as 0.1 μA in the case where the potential difference between the source electrode 13a and the drain electrode 13b is 1 V.
In short, in order to reduce the off-state current, the electron concentration on the side opposite to the gate needs to be prevented from being such an unignorable value. For that purpose, a method in which the thickness of the semiconductor layer 11 is reduced can be considered. In other words, a region which is not influenced by the gate 15 may be reduced. In the case of the FET in the drawing, calculation results indicate that the off-state current can be reduced to one hundred-thousandth when the thickness of the semiconductor layer 11 is reduced by half, for example.
However, in an extremely small device in which the distance between the source electrode 13a and the drain electrode 13b is 24 nm, for example, the thickness of the semiconductor layer 11 needs to be less than or equal to 2.5 nm and thus it is technically difficult to uniformly form the semiconductor layer 11 with such a small thickness. Moreover, reduction in the thickness of the semiconductor layer 11 leads to smaller on-state current.
A second method is to make the gate insulating film 14 thinner. When the thickness of the gate insulating film 14 in the drawing is reduced to one sixth or less, the influence of the gate 15 can reach the back surface of the semiconductor layer 11. However, as in the above example, when the distance between the source electrode 13a and the drain electrode 13b is 24 nm, the gate insulating film 14 needs to have a thickness of less than or equal to 0.8 nm.
A gate insulating film is formed over an oxide semiconductor by a sputtering method or a CVD method. It is difficult to form, by these methods, an insulating film having high quality and a uniform thickness like an insulating film of silicon formed by a thermal oxidation method; therefore, these methods are not realistic.
The above consideration is based on the premise that the force of the source electrode 13a or the drain electrode 13b for injecting electrons into the semiconductor layer 11 is equal to the force of the gate 15 for eliminating electrons from the semiconductor layer 11. When the former force is stronger than the latter force, more electrons are injected from the source electrode 13a or the drain electrode 13b into the semiconductor layer 11.